Design and Implementation of Uart with Bist for Low Power Dissipation Using Lp-Tpg
نویسنده
چکیده
The main aim of this paper is to design and implement efficient UART and test the UART with built in self testing technique . A new Test pattern generator is simulated and used in BIST architecture in order to reduce power dissipation. As we know that power dissipation is more during the test mode than in normal mode hence In this project the pattern generator used is the low power pattern generator in order to reduce the power dissipation during test mode. The project is synthesized using Xilinx 14.5 design suite
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